module riscv32 #(
	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0008,
	parameter [31:0] STACKADDR = 32'h ffff_ffff,
	parameter CLK_FREQ=5000000,	//系统时钟频率
	parameter UART_BPS=9600
) (
	input clk, resetn,
	output trap,

	output         mem_valid,
	output         mem_instr,
	input          mem_ready,

	output  [31:0] mem_addr,
	output  [31:0] mem_wdata,
	output  [ 3:0] mem_wstrb,
	input   [31:0] mem_rdata,
	input tlb_cached,
	// IRQ Interface
	input   [31:0] irq,
	output  [31:0] eoi,

    output  [31:0] PC,
	// Trace Interface
	output         trace_valid,
	output  [35:0] trace_data,
    output cpu_reset_out,
	input dbg_uart_rx,
	output dbg_uart_tx//

);
wire [31:0] cpu_mem_addr;
wire [31:0] cpu_mem_wdata;
wire [3:0]  cpu_mem_wstrb;
wire 		cpu_mem_ready;
wire [31:0] cpu_mem_rdata;
wire 		cpu_mem_valid;
wire		cpu_mem_instr;

wire [31:0] dbg_mem_addr;
wire [31:0] dbg_mem_wdata;
wire [3:0]  dbg_mem_wstrb;
wire 		dbg_mem_ready;
wire [31:0] dbg_mem_rdata;
wire 		dbg_mem_valid;

wire cpu_halt_resp;
wire cpu_halt_req;
wire step_req;
wire cpu_run_req;

wire dbg_reg_write_req;
wire dbg_reg_write_resp;
wire [31:0] dbg_reg_wdata;
wire [7:0] dbg_reg_raddr;
wire [7:0] dbg_reg_waddr;
wire [31:0]  dbg_reg_data_out;
wire [11:0] dbg_csr_reg_addr;
wire dbg_crs_reg_wr;
wire dbg_csr_we_resp;
wire [31:0] dbg_csr_data_out;
wire [31:0] dbg_csr_data_in;
mem_mux mem_mux_u1(
	.clk(clk),
    .resetn(resetn),
    .cpu_mem_addr (cpu_mem_addr ),
    .cpu_mem_wdata(cpu_mem_wdata),
    .cpu_mem_wstrb(cpu_mem_wstrb),
    .cpu_mem_ready(cpu_mem_ready),
    .cpu_mem_rdata(cpu_mem_rdata),
    .cpu_mem_valid(cpu_mem_valid),
    .cpu_mem_instr(cpu_mem_instr),
    
    .dbg_mem_addr(dbg_mem_addr),
    .dbg_mem_wdata(dbg_mem_wdata),
    .dbg_mem_wstrb(dbg_mem_wstrb),
    .dbg_mem_ready(dbg_mem_ready),
    .dbg_mem_rdata(dbg_mem_rdata),
    .dbg_mem_valid(dbg_mem_valid),

    .slave_mem_addr(mem_addr),
    .slave_mem_wdata(mem_wdata),
    .slave_mem_wstrb(mem_wstrb),
    .slave_mem_ready(mem_ready),
    .slave_mem_rdata(mem_rdata),
    .slave_mem_valid(mem_valid),
    .slave_mem_instr(mem_instr)
);
uart_debug #(
	.CLK_FREQ	(CLK_FREQ),
	.UART_BPS	(UART_BPS)
)uart_debug_u1(
	.clk(clk),
    .resetn(resetn),
    .reset_out(),

    .uart_rx(dbg_uart_rx),
    .uart_tx(dbg_uart_tx),
    .mem_addr(dbg_mem_addr),
    .mem_wdata(dbg_mem_wdata),
    .mem_wstrb(dbg_mem_wstrb),
    .mem_valid(dbg_mem_valid),
    .mem_rdata(dbg_mem_rdata),
    .mem_ready(dbg_mem_ready),
	.halt_req(cpu_halt_req),
	.run_req(cpu_run_req),
	.step_req(step_req),
	.halt_signal(cpu_halt_resp),
    .reg_addr(reg_addr),
	.dbg_reg_write_req(dbg_reg_write_req),
	.dbg_reg_write_resp(dbg_reg_write_resp),
	.dbg_reg_wdata(dbg_reg_wdata),
	.dbg_reg_raddr(dbg_reg_raddr),
	.dbg_reg_waddr(dbg_reg_waddr),
	.dbg_reg_data_out(dbg_reg_data_out),
	.dbg_csr_reg_addr(dbg_csr_reg_addr),
	.dbg_crs_reg_wr(dbg_crs_reg_wr),
	.dbg_csr_we_resp(dbg_csr_we_resp),
	.dbg_csr_data_out(dbg_csr_data_out),
	.dbg_csr_data_in(dbg_csr_data_in),
    .cpu_reset_out(cpu_reset_out)
);

riscv32_alu #(
	.MASKED_IRQ(MASKED_IRQ),
	.LATCHED_IRQ(LATCHED_IRQ),
	.PROGADDR_RESET(PROGADDR_RESET),
	.PROGADDR_IRQ(PROGADDR_IRQ),
	.STACKADDR(STACKADDR)
) riscv32_alu_u1(
	.clk(clk),
    .resetn(resetn),
	.mem_valid(cpu_mem_valid),
	.mem_instr(cpu_mem_instr),
	.mem_ready(cpu_mem_ready),

	.mem_addr(cpu_mem_addr),
	.mem_wdata(cpu_mem_wdata),
	.mem_wstrb(cpu_mem_wstrb),
	.mem_rdata(cpu_mem_rdata),
	.tlb_cache(tlb_cached),
	// IRQ Interface
	.irq({3'd0,time_irq,irq[27:0]}),
	.irq_state(trap),

	// Trace Interface
	.run_req(cpu_run_req),
	.step_req(step_req),
	.halt_req(cpu_halt_req),
	.halt_ready(cpu_halt_resp),

	.dbg_reg_write_req(dbg_reg_write_req),
    .dbg_reg_write_resp(dbg_reg_write_resp),
    .dbg_reg_wdata(dbg_reg_wdata),
    .dbg_reg_raddr(dbg_reg_raddr),
    .dbg_reg_waddr(dbg_reg_waddr),
    .dbg_reg_data_out(dbg_reg_data_out),
    .dbg_csr_reg_addr(dbg_csr_reg_addr),
    .dbg_crs_reg_wr(dbg_crs_reg_wr),
    .dbg_csr_we_resp(dbg_csr_we_resp),
    .dbg_csr_data_out(dbg_csr_data_out),
    .dbg_csr_data_in(dbg_csr_data_in),
	.dbg_reset(cpu_reset_out),
	.mret(),
	.mcause_o(),
    .mie()

);
endmodule
